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ds07-13735-2ea fujitsu microelectronics data sheet ?check sheet? is seen at the following support page url : http://edevice.fujitsu.com/micom/en-support/ ?check sheet? lists the minimal requirement items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest caut ions on development. copyright?2004-2008 fujitsu microelec tronics limited all rights reserved 2007.10 16-bit microcontroller cmos f 2 mc-16lx MB90335 series mb90337/f337/v330a description the MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require usb communications. the usb feature supports not only 12-mbps function operation but also mini-host operation. it is equip ped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support usb communications. while inheriting the at architecture of the f 2 mc* family, the instruction set supports the c language and extended addressing modes and contains enhanced signed multiplicat ion and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, long word processing is now available by intro- ducing a 32-bit accumulator. note : f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ? clock built-in oscillation circuit and pll clock frequency multiplication circuit oscillation clock the main clock is the oscillation clock divi ded into 2 (for oscilla tion 6 mhz : 3 mhz) clock for usb is 48 mhz machine clock frequency of 6 mhz, 12 mhz or 24 mhz selectable minimum execution time of instruction : 41.6 ns (6 mhz oscillation clock, 4-time multiplied : machine clock 24 mhz and at operating v cc = 3.3 v) ? the maximum memory space:16 mbytes ? 24-bit addressing ? bank addressing (continued)
MB90335 series 2 (continued) ? instruction system data types: bit, byte, word, long word addressing mode (23 types) enhanced high-precision computing with 32-bit accumulator enhanced multiply/divide instructions with sign an d the reti instruction ? instruction system compatible with high-level language (c language) and multi-task employing system stack pointer instruction set symmetry and barrel shift instructions ? program patch function (2 address pointer) ? 4-byte instruction queue ? interrupt function priority levels are programmable 20 interrupts function ? data transfer function extended intelligent i/o service function (ei 2 os) : maximum of 16 channels dmac : maximum 16 channels ? low power consumption mode sleep mode (with the cpu operating clock stopped) time-base timer mode (wit h the oscillator clock and time-base timer operating) stop mode (with the os cillator clock stopped) cpu intermittent operation mode (with the cpu operating at fixed intervals of set cycles) ? package lqfp-64p (fpt-64p-m09 : 0.65 mm pin pitch) ? process : cmos technology ? operation guaranteed temperature: ? 40 c to + 85 c (0 c to + 70 c when usb is in use)
MB90335 series 3 internal peripheral function (resource) ? i/o port : max 45 ports ? time-base ti mer : 1channel ? watchdog timer : 1 channel ? 16-bit reload timer : 1 channel ? multi-functional timer 8/16-bit ppg timer (8-bit 4 channels or 16-bit 2 channels) the period and duty of the output pulse can be set by the program. 16-bit pwc timer : 1 channel timer function and pulse width measurement function ? uart : 2 channels equipped with full duplex doub le buffer with 8-bit length asynchronous transfer or clock-synchronous serial (extended i/o serial) transfer can be set. ? extended i/o serial interface : 1 channel ? dtp/external interrupt circuit (8 channels) activate the extended intelligent i/o service by external interrupt input interrupt output by external interrupt input ? delayed interrupt output module output an interrupt request for task switching ? usb : 1 channel usb function (conform to usb 2.0 full speed) full speed is supported/endpoint are specifiable up to six. dual port ram (the fifo mode is supported). transfer type: control, interrupt, bulk or isochronous transfer possible usb mini-host function ? i 2 c* interface : 1 channel supports intel sm bus standards and phillips i 2 c bus standards two-wire data transfer protocol specification master and slave transmission/reception * : i 2 c license : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by phillips.
MB90335 series 4 product lineup * : it is setting of jumper switch (tool vcc) when emulator (mb2147-01) is used. please refer to the mb2147-01 or mb2147-20 hardware manual (3.3 emulator-dedicated power supply switching) about details. packages and product models : yes : no part number mb90v330a mb90f337 mb90337 type for evaluation built-in flash memory built-in mask rom rom capacity no 64 kbytes ram capacity 28 kbytes 4 kbytes emulator-specific power supply * used bit ? cpu functions number of basic instructions minimum instruction execution time addressing type program patch function maximum memory space : 351 instructions : 41.6 ns / at oscillation of 6 mhz (when 4 times are used : machine clock of 24 mhz) : 23 types : for 2 address pointers : 16 mbytes ports i/o ports(cmos) 45 ports uart equipped with full-duplex double buffer clock synchronous or asynchronous operation selectable. it can also be used for i/o serial. built-in special baud-rate generator built-in 2 channels 16-bit reload timer 16-bit reload timer operation built-in 1 channel multi-functional timer 8/16-bit ppg timer (8-bit mode 4 channels, 16-bit mode 2 channels) 16-bit pwc timer 1 channel dtp/external interrupt 8 channels interrupt factor : ?l? ?h? edge /?h? ?l? edge /?l? level /?h? level selectable i 2 c 1 channel extended i/o serial interface 1 channel usb 1 channel usb function (conform to usb 2.0 full speed) usb mini-host function withstand voltage of 5 v 8 ports (excluding utest and i/o for i 2 c) low power consumption mode sleep mode/timebase timer mode/stop mode/cpu intermittent mode process cmos operating voltage v cc 3.3 v 0.3 v (at maximum ma chine clock 24 mhz) package mb90337 mb90f337 mb90v330a fpt-64p-m09 (lqfp-0.65 mm) pga-299c-a01 (pga)
MB90335 series 5 pin assignment (top view) (fpt-64p-m09) ute s t v ss dvm dvp vcc v ss hvm hvp vcc hcon p42/ s in0 p4 3 / s ot0 p44/ s ck0 p45/ s in1 p46/ s ot1 p47/ s ck1 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 4 8 47 46 45 44 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 v ss x1 x0 p24/ppg0 p2 3 p22 p21 p20 p17 p16 p15 p14 p1 3 p12 p11 p10 64 6 3 62 61 60 59 5 8 57 56 55 54 5 3 52 51 50 49 p51 p41/tot0 p40/tin0 p67/int7/ s da0 p66/int6/ s cl0 p65/int5/pwc p64/int4/ s ck p6 3 /int 3 / s ot p62/int2/ s in p61/int1 p60/int0 p27/ppg 3 p26/ppg2 p25/ppg1 p50 vcc 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 p52 p5 3 v ss md2 md1 md0 r s t p54 p00 p01 p02 p0 3 p04 p05 p06 p07
MB90335 series 6 pin description (continued) pin no. pin name i/o circuit type* status at reset/ function function 46 , 47 x0, x1 a oscillation status it is a terminal which connects the oscillator. when connecting an external clock, leave the x1 pin side unconnected. 23 rst f reset input external reset input pin. 25 to 32 p00 to p07 i port input (hi-z) general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd00 to rd07 = 1) by the pull-up resistor setting register (rdr0). (when the po wer output is set, it is invalid.) 33 to 40 p10 to p17 i general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd10 to rd17 = 1) by the pull-up resistor setting register (rdr1). (when the po wer output is set, it is invalid.) 41 to 44 p20 to p23 d general purpose input/output port. 45 p24 d general purpose input/output port. ppg0 functions as output pins of ppg timers ch.0. 51 to 53 p25 to p27 d general purpose input/output port. ppg1 to ppg3 functions as output pins of ppg timers ch.1 to ch.3. 62 p40 h general purpose input/output port. tin0 function as event input pin of 16-bit reload timer. 63 p41 h general purpose input/output port. tot0 function as output pin of 16-bit reload timer. 11 p42 h general purpose input/output port. sin0 functions as a data input pin for uart ch.0. 12 p43 h general purpose input/output port. sot0 functions as a data output pin for uart ch.0. 13 p44 h general purpose input/output port. sck0 functions as a clock i/o pin for uart ch.0. 14 p45 h general purpose input/output port. sin1 functions as a data input pin for uart ch.1. 15 p46 h general purpose input/output port. sot1 functions as a data output pin for uart ch.1. 16 p47 h general purpose input/output port. sck1 functions as a clock i/o pin for uart ch.1. 50 p50 k general purpose input/output port. 64 p51 k general purpose input/output port. 17, 18 p52, p53 k general purpose input/output port. 24 p54 k general purpose input/output port.
MB90335 series 7 (continued) * : for circuit information, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* status at reset/ function function 54, 55 p60, p61 c port input (hi-z) general purpose input/output port (withstand voltage of 5 v) . int0, int1 functions as the input pin for external interrupt ch.0 and ch.1. 56 p62 c general purpose input/output port (withstand voltage of 5 v) . int2 functions as the input pin for external interrupt ch.2. sin data input pin for extended i/o serial interface. 57 p63 c general purpose input/output port (withstand voltage of 5 v) . int3 functions as the input pin for external interrupt ch.3. sot data output pin for extended i/o serial interface. 58 p64 c general purpose input/output port (withstand voltage of 5 v) . int4 functions as the input pin for external interrupt ch.4. sck clock i/o pin for extended i/o serial interface. 59 p65 c general purpose input/output port (withstand voltage of 5 v) . int5 functions as the input pin for external interrupt ch.5. pwc functions as the pwc input pin. 60 p66 c general purpose input/output port (withstand voltage of 5 v) . int6 functions as the input pin for external interrupt ch.6. scl0 functions as the input/output pin for i 2 c interface clock. the port output must be placed in hi-z state during i 2 c interface operation. 61 p67 c general purpose input/output port (withstand voltage of 5 v) . int7 functions as the input pin for external interrupt ch.7. sda0 functions as the i 2 c interface data input/output pin. the port out- put must be placed in hi-z state during i 2 c interface operation. 1 utest c utest input usb test pin. connect this to a pull-down resistor during normal usage. 3dvmj usb input (suspend) usb function d ? pin. 4 dvp j usb function d + pin. 7 hvm j usb mini-host d ? pin. 8 hvp j usb mini-host d + pin. 10 hcon e high output external pull-up resistor connection pin. 21, 22 md1, md0 b mode input input pin for selecting operation mode. 20 md2 g 5vcc ? power supply power supply pin. 9vcc ? power supply pin. 49 vcc ? power supply pin. 2vss ? power supply pin (gnd). 6vss ? power supply pin (gnd). 19 vss ? power supply pin (gnd). 48 vss ? power supply pin (gnd).
MB90335 series 8 i/o circuit type (continued) type circuit remarks a oscillation feedback resistor of approx. 1 m ? with standby control b cmos hysteresis input c cmos hysteresis input n-ch open drain output d cmos output cmos hysteresis input (with input interception function at standby) notes : ? share one output buffer because both output of i/o port and internal resource are used. ? share one input buffer because both input of i/o port and internal resource are used. e cmos output f cmos hysteresis input with pull-up resistor g cmos hysteresis input with pull-down resistor of approx. 50 k ? flash product is not provided with pull- down resistor. x1 x0 standby control signal clock input cmos hysteresis input nout n-ch cmos hysteresis input standby control signal pout nout p-ch n-ch cmos hysteresis input standby control signal pout nout p-ch n-ch r cmos hysteresis input r cmos hysteresis input
MB90335 series 9 (continued) type circuit remarks h cmos output cmos hysteresis input (with input interception function at standby) with open drain control signal i cmos output cmos input (with input interception function at standby) programmable input pull-up resistor j usb i/o pin k cmos output cmos input (with input interception function at standby) pout nout p-ch n-ch open drain control signal standby control signal cmos hysteresis input pout nout p-ch n-ch ctl r cmos input standby control signal d + d ? d + input d - input differential input full d + output full d - output low d + output low d - output direction speed pout nout p-ch n-ch cmos input standby control signal
MB90335 series 10 handling devices 1. preventing latch-up and turning on power supply latch-up may occur on cmos ic under the following conditions: ? if a voltage higher than v cc or lower than v ss is applied to input and output pins. ? a voltage higher than the rated voltage is applied between v cc and v ss . when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. when using cmos ic, take great care to prevent the occurrence of latch-up. 2. treatment of unused pins leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent dam- age. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. if there is unused output pin, make it to open. 3. about the attention when the external clock is used even when using an external clock si gnal, an oscillation stab ilization delay is applied af ter a power-on reset or when recovering from sub-clock or stop mode. when suing an external clock, 25 mhz should be the upper frequency limit. the following figure shows a sample use of external clock signals. 4. treatment of power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cerami c bypass capacitor of approximately 0.1 f between v cc and v ss pins near this device. 5. about crystal oscillator circuit noise near the x0 and x1 pins may cause the device to malfunction. design the printed circuit board so that x0, x1, the crystal oscillator (or cerami c oscillator) , and the bypass capacito r to ground are located as close to the device as possible. it is strongly recommended to design the pc board artwork with the x0 and x1 pins surrounded by ground plane because stable operation can be expected with such a layout. please ask the crystal maker to evaluate the oscillati onal characteristics of the crystal and this device. 6. caution on operations during pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external re ference clock input stops while the pll clock mode is selected, a self -oscillator circuit contained in the pl l may continue its operation at its self-running frequency. however, fujitsu microelectronics will not guarantee re sults of operations if such failure occurs. x0 x1 open using external clock
MB90335 series 11 7. stabilization of supply voltage a sudden change in the supply voltage may cause the device to malfunction even within the v cc supply voltage operating range. for stabilization reference, the supply voltage sh ould be stabilized so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 mhz to 60 mhz) fall below 10 % of the standard v cc supply voltage and the transient regulation does not exceed 0.1 v/ms at temporary changes such as power supply switching. 8. writing to flash memory for serial writing to flash memory, always make sure that the operating voltage v cc is between 3.13 v and 3.6 v. for normal writing to flash memory, always make sure that the operating voltage v cc is between 3.0 v and 3.6 v.
MB90335 series 12 block diagram f 2 mc-16lx cpu ram rom uart/sio ch.0, ch.1 i 2 c sio dmac usb (function) (mini-host) p00 p07 p10 p17 p20 p27 p40 p47 p50 p54 p60 p67 x0, x1 rst md0 to md2 sin0, sin1 sot0, sot1 sck0, sck1 scl0 sda0 int0 to int7 dvp dvm hvp hvm hcon utest tot0 tin0 ppg0 to ppg3 pwc sin sot sck * : channel for use in 8-bit mode. 2 channels (ch.1, ch.3) are used in 16-bit mode. note : i/o ports share pins with peripheral function (resources) . for details, refer to ? pin assignment? and ? pin description?. note also that pins used for peripheral function (resources) cannot serve as i/o ports. 16-bit reload timer external interrupt 16-bit pwc 8/16-bit ppg timer ch.0 to ch.3* clock control circuit interrupt controller internal data bus i/o port (port 0, 1, 2, 4, 5, 6)
MB90335 series 13 memory map notes : ? when the rom mirror function register has been set, the mirror image data at upper addresses (?ff8000 h to ffffff h ? ) of bank ff is visible from the upper addresses (?008000 h to 00ffff h ?) of bank 00. ? the rom mirror function is effective for using the c compiler small model. ? the lower 16-bit addresses of bank ff are equivalent to those of bank 00. since the rom area in bank ff exceeds 48 kbytes, however, the mirror image of all the data in the rom area cannot be reproduced in bank 00. ? when the c compiler small model is used, the data table mirror image can be shown at ?008000 h to 00ffff h ? by storing the data table at ?ff8000 h to ffffff h ?. therefore, data tables in the rom area can be referred without declaring the far addressing with the pointer. ffffff h 00ffff h 007fff h 007900 h 007100 h 00 8 000 h ff0000 h 000100 h 0000fb h 000000 h ffffff h 00ffff h 007fff h 007900 h 001100 h 00 8 000 h ff0000 h 000100 h 0000fb h 000000 h ffffff h 00ffff h 007fff h 007900 h 001100 h 00 8 000 h ff0000 h 000100 h 0000fb h 000000 h mb90v 33 0a mb90f 33 7 mb90 33 7 regi s ter regi s ter regi s ter single chip mode (with rom mirror function) peripheral area rom (ff bank) rom area (image of ff bank) ram area (28 kbytes) peripheral area peripheral area rom (ff bank) rom area (image of ff bank) ram area (4 kbytes ) peripheral area peripheral area rom (ff bank) rom area (image of ff bank) ram area (4 kbytes ) peripheral area
MB90335 series 14 f 2 mc - 16l cpu programming model dedicated register general purpose registers processor status ah al dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16-bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 msb lsb ilm 15 13 ps rp ccr 12 8 70 bit
MB90335 series 15 i/o map (continued) address register abbreviation register read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h prohibited 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 - - - xxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h to 00000f h prohibited 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h prohibited 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 - - - 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h to 00001a h prohibited 00001b h odr4 port 4 output pin register r/w port 4 (open-drain control) 0 0 0 0 0 0 0 0 b 00001c h rdr0 port 0 pull-up resistance register r/w port 0 (pull-up) 0 0 0 0 0 0 0 0 b 00001d h rdr1 port 1 pull-up resistance register r/w port 1 (pull-up) 0 0 0 0 0 0 0 0 b 00001e h prohibited 00001f h 000020 h smr0 serial mode register 0 r/w uart0 0 0 1 0 0 0 0 0 b 000021 h scr0 serial control register 0 r/w 0 0 0 0 0 1 0 0 b 000022 h sidr0 serial input data register 0 r xxxxxxxx b sodr0 serial output data register 0 w 000023 h ssr0 serial status register 0 r/w 0 0 0 0 1 0 0 0 b 000024 h utrlr0 uart prescaler reload register 0 r/w communication prescaler (uart0) 0 0 0 0 0 0 0 0 b 000025 h utcr0 uart prescaler control register 0 r/w 0 0 0 0 - 0 0 0 b 000026 h smr1 serial mode register 1 r/w uart1 0 0 1 0 0 0 0 0 b 000027 h scr1 serial control register 1 r/w 0 0 0 0 0 1 0 0 b 000028 h sidr1 serial input data register 1 r xxxxxxxx b sodr1 serial output data register 1 w 000029 h ssr1 serial status register 1 r/w 0 0 0 0 1 0 0 0 b
MB90335 series 16 (continued) address register abbreviation register read/ write resource name initial value 00002a h utrlr1 uart prescaler reload register 1 r/w communication prescaler (uart1) 0 0 0 0 0 0 0 0 b 00002b h utcr1 uart prescaler control register 1 r/w 0 0 0 0 - 0 0 0 b 00002c h to 00003b h prohibited 00003c h enir dtp/interrupt enable register r/w dtp/external interrupt 0 0 0 0 0 0 0 0 b 00003d h eirr dtp/interrupt source register r/w 0 0 0 0 0 0 0 0 b 00003e h elvr request level setting register lower r/w 0 0 0 0 0 0 0 0 b 00003f h request level setting register upper r/w 0 0 0 0 0 0 0 0 b 000040 h to 000045 h prohibited 000046 h ppgc0 ppg0 operation mode control register r/w ppg ch.0 0x0 0 0xx1 b 000047 h ppgc1 ppg1 operation mode control register r/w ppg ch.1 0x0 0 0 0 0 1 b 000048 h ppgc2 ppg2 operation mode control register r/w ppg ch.2 0x0 0 0xx1 b 000049 h ppgc3 ppg3 operation mode control register r/w ppg ch.3 0x0 0 0 0 0 1 b 00004a h prohibited 00004b h 00004c h ppg01 ppg0 and ppg1 output control register r/w ppg ch.0/ch.1 0 0 0 0 0 0xx b 00004d h prohibited 00004e h ppg23 ppg2 and ppg3 output control register r/w ppg ch.2/ch.3 0 0 0 0 0 0 xx b 00004f h to 000057 h prohibited 000058 h smcs serial mode control status register r/w extended serial i/o xxxx0 0 0 0 b 000059 h 0 0 0 0 0 0 1 0 b 00005a h sdr serial data register r/w xxxxxxxx b 00005b h sdcr communication pr escaler control register r/w communication prescaler 0xxx0 0 0 0 b 00005c h pwcsr pwc control status register r/w 16-bit pwc timer 0 0 0 0 0 0 0 0 b 00005d h 0 0 0 0 0 0 0 x b 00005e h pwcr pwc data bu ffer register r/w 0 0 0 0 0 0 0 0 b 00005f h 0 0 0 0 0 0 0 0 b 000060 h divr pwc dividing ratio control register r/w - - - - - - 0 0 b 000061 h prohibited 000062 h tmcsr0 timer control status register r/w 16-bit reload timer 0 0 0 0 0 0 0 0 b 000063 h xxxx 0 0 0 0 b 000064 h tmr0 16-bit timer register lower r xxxxxxxx b tmrlr0 16-bit reload register lower w xxxxxxxx b 000065 h tmr0 16-bit timer register upper r xxxxxxxx b tmrlr0 16-bit reload register upper w xxxxxxxx b
MB90335 series 17 (continued) address register abbreviation register read/ write resource name initial value 000066 h to 00006e h prohibited 00006f h romm rom mirroring function selection register w rom mirror function selection module - - - - - - 1 1 b 000070 h ibsr0 i 2 c bus status register r i 2 c bus interface 0 0 0 0 0 0 0 0 b 000071 h ibcr0 i 2 c bus control register r/w 0 0 0 0 0 0 0 0 b 000072 h iccr0 i 2 c bus clock control register r/w xx 0 xxxxx b 000073 h iadr0 i 2 c bus address register r/w xxxxxxxx b 000074 h idar0 i 2 c bus data register r/w xxxxxxxx b 000075 h to 00009a h prohibited 00009b h dcsr dma descriptor cha nnel specification register r/w dmac 0 0 0 0 0 0 0 0 b 00009c h dsrl dma status register lower r/w 0 0 0 0 0 0 0 0 b 00009d h dsrh dma status register upper r/w 0 0 0 0 0 0 0 0 b 00009e h pacsr program address detection control status register r/w address match detection 0 0 0 0 0 0 0 0 b 00009f h dirr delayed interrupt source generate/ release register r/w delayed interrupt - - - - - - - 0 b 0000a0 h lpmcr low power consumption mode control register r/w low power consumption control circuit 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selection register r/w clock 1 1 1 1 1 1 0 0 b 0000a2 h prohibited 0000a3 h 0000a4 h dssr dma stop status register r/w dmac 0 0 0 0 0 0 0 0 b 0000a5 h to 0000a7 h prohibited 0000a8 h wdtc watchdog timer control regist er r/w watchdog timer x - xxx 1 1 1 b 0000a9 h tbtc time-base timer control register r/w time-base timer 1 - - 0 0 1 0 0 b 0000aa h prohibited 0000ab h 0000ac h derl dma enable register lower r/w dmac 0 0 0 0 0 0 0 0 b 0000ad h derh dma enable register upper r/w 0 0 0 0 0 0 0 0 b 0000ae h fmcs flash memory control status register r/w flash memory i/f 0 0 0 x 0 0 0 0 b 0000af h prohibited
MB90335 series 18 (continued) address register abbreviation register read/ write resource name initial value 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h hcnt0 host control register 0 r/w usb mini-host 0 0 0 0 0 0 0 0 b 0000c1 h hcnt1 host control register 1 r/w 0 0 0 0 0 0 0 1 b 0000c2 h hirq host interruption register r/w 0 0 0 0 0 0 0 0 b 0000c3 h herr host error status register r/w 0 0 0 0 0 0 1 1 b 0000c4 h hstate host state status register r/w xx 0 1 0 0 1 0 b 0000c5 h hfcomp sof interrupt frame compare reg- ister r/w 0 0 0 0 0 0 0 0 b 0000c6 h hrtimer retry timer setting register r/w 0 0 0 0 0 0 0 0 b 0000c7 h r/w 0 0 0 0 0 0 0 0 b 0000c8 h r/w xxxxxx 0 0 b 0000c9 h hadr host address register r/w x 0 0 0 0 0 0 0 b 0000ca h heof eof setting register r/w 0 0 0 0 0 0 0 0 b 0000cb h r/w xx 0 0 0 0 0 0 b 0000cc h hframe frame setting register r/w 0 0 0 0 0 0 0 0 b 0000cd h r/w xxxxx 0 0 0 b 0000ce h htoken host token end point register r/w 0 0 0 0 0 0 0 0 b 0000cf h prohibited 0000d0 h udcc udc control register r/w usb function 1 0 1 0 0 0 0 0 b 0000d1 h r/w 0 0 0 0 0 0 0 0 b
MB90335 series 19 (continued) address register abbreviation register read/ write resource name initial value 0000d2 h ep0c ep0 control register r/w usb function 0 1 0 0 0 0 0 0 b 0000d3 h r/w xxxx 0 0 0 0 b 0000d4 h ep1c ep1 control register r/w 0 0 0 0 0 0 0 0 b 0000d5 h r/w 0 1 1 0 0 0 0 1 b 0000d6 h ep2c ep2 control register r/w 0 1 0 0 0 0 0 0 b 0000d7 h r/w 0 1 1 0 0 0 0 0 b 0000d8 h ep3c ep3 control register r/w 0 1 0 0 0 0 0 0 b 0000d9 h r/w 0 1 1 0 0 0 0 0 b 0000da h ep4c ep4 control register r/w 0 1 0 0 0 0 0 0 b 0000db h r/w 0 1 1 0 0 0 0 0 b 0000dc h ep5c ep5 control register r/w 0 1 0 0 0 0 0 0 b 0000dd h r/w 0 1 1 0 0 0 0 0 b 0000de h tmsp time stamp register r 0 0 0 0 0 0 0 0 b 0000df h r xxxxx0 0 0 b 0000e0 h udcs udc status register r/w xx0 0 0 0 0 0 b 0000e1 h udcie udc interrupt enable register r/w 0 0 0 0 0 0 0 0 b 0000e2 h ep0is ep0i status register r/w xxxxxxxx b 0000e3 h r/w 1 0 xxx 1 xx b 0000e4 h ep0os ep0o status register r/w, r 0 xxxxxxx b 0000e5 h r/w 1 0 0 xx 0 0 0 b 0000e6 h ep1s ep1 status register r xxxxxxxx b 0000e7 h r/w 1 0 0 0 0 0 0 x b 0000e8 h ep2s ep2 status register r xxxxxxxx b 0000e9 h r/w 1 0 0 0 0 0 0 0 b 0000ea h ep3s ep3 status register r xxxxxxxx b 0000eb h r/w 1 0 0 0 0 0 0 0 b 0000ec h ep4s ep4 status register r xxxxxxxx b 0000ed h r/w 1 0 0 0 0 0 0 0 b 0000ee h ep5s ep5 status register r xxxxxxxx b 0000ef h r/w 1 0 0 0 0 0 0 0 b 0000f0 h ep0dt ep0 data register r/w xxxxxxxx b 0000f1 h r/w xxxxxxxx b 0000f2 h ep1dt ep1 data register r/w xxxxxxxx b 0000f3 h r/w xxxxxxxx b 0000f4 h ep2dt ep2 data register r/w xxxxxxxx b 0000f5 h r/w xxxxxxxx b 0000f6 h ep3dt ep3 data register r/w xxxxxxxx b 0000f7 h r/w xxxxxxxx b 0000f8 h ep4dt ep4 data register r/w xxxxxxxx b 0000f9 h r/w xxxxxxxx b
MB90335 series 20 (continued) address register abbreviation register read/ write resource name initial value 0000fa h ep5dt ep5 data register r/w usb function xxxxxxxx b 0000fb h r/w xxxxxxxx b 0000fc h to 0000ff h prohibited 000100 h to 001100 h ram area 001ff0 h padr0 program address detection register ch.0 lower r/w address match detection xxxxxxxx b 001ff1 h program address detection register ch.0 middle r/w xxxxxxxx b 001ff2 h program address detection register ch.0 upper r/w xxxxxxxx b 001ff3 h padr1 program address detection register ch.1 lower r/w xxxxxxxx b 001ff4 h program address detection register ch.1 middle r/w xxxxxxxx b 001ff5 h program address detection register ch.1 upper r/w xxxxxxxx b 007900 h prll0 ppg reload register lower ch.0 r/w ppg ch.0 xxxxxxxx b 007901 h prlh0 ppg reload register upper ch.0 r/w xxxxxxxx b 007902 h prll1 ppg reload register lower ch.1 r/w ppg ch.1 xxxxxxxx b 007903 h prlh1 ppg reload register upper ch.1 r/w xxxxxxxx b 007904 h prll2 ppg reload register lower ch.2 r/w ppg ch.2 xxxxxxxx b 007905 h prlh2 ppg reload register upper ch.2 r/w xxxxxxxx b 007906 h prll3 ppg reload register lower ch.3 r/w ppg ch.3 xxxxxxxx b 007907 h prlh3 ppg reload register upper ch.3 r/w xxxxxxxx b 007908 h to 00790b h prohibited 00790c h fwr0 flash memory program control register 0 r/w flash 0 0 0 0 0 0 0 0 b 00790d h fwr1 flash memory program control register 1 r/w flash 0 0 0 0 0 0 0 0 b 00790e h ssr0 sector conversion sett ing register r/w flash 0 0 xxxxx0 b 00790f h to 00791f h prohibited
MB90335 series 21 (continued) explanation on read/write explanation of initial values note : no i/o instruction can be used for registers located between 007900 h and 007fff h . address register abbreviation register read/ write resource name initial value 007920 h dbapl dma buffer address pointer lower 8-bit r/w dmac xxxxxxxx b 007921 h dbapm dma buffer address pointer middle 8-bit r/w xxxxxxxx b 007922 h dbaph dma buffer address po inter upper 8-bit r/w xxxxxxxx b 007923 h dmacs dma control register r/w xxxxxxxx b 007924 h dioal dma i/o register address pointer lower 8-bit r/w xxxxxxxx b 007925 h dioah dma i/o register address pointer upper 8-bit r/w xxxxxxxx b 007926 h ddctl dma data counter lower 8-bit r/w xxxxxxxx b 007927 h ddcth dma data counter upper 8-bit r/w xxxxxxxx b 007928 h to 007fff h prohibited r/w : readable and writable r : read only w : write only 0 : initial value is ?0?. 1 : initial value is ?1?. x : initial value is undefined. - : initial value is undefined (none).
MB90335 series 22 interrupt sources, interrupt vectors, and interrupt control registers (continued) interrupt source ei 2 os support dmac interrupt vector interrupt control register priority number* 1 address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? usb function1 0, 1 #11 0b h ffffd0 h icr00 0000b0 h usb function2 2 to 6* 2 #12 0c h ffffcc h usb function3 #13 0d h ffffc8 h icr01 0000b1 h usb function4 #14 0e h ffffc4 h usb mini-host1 #15 0f h ffffc0 h icr02 0000b2 h usb mini-host2 #16 10 h ffffbc h i 2 c ch.0 #17 11 h ffffb8 h icr03 0000b3 h dtp/external interrupt ch.0/ch.1 #18 12 h ffffb4 h no ?? #19 13 h ffffb0 h icr04 0000b4 h dtp/external interrupt ch.2/ch.3 #20 14 h ffffac h no ?? #21 15 h ffffa8 h icr05 0000b5 h dtp/external interrupt ch.4/ch.5 #22 16 h ffffa4 h pwc/reload timer ch.0 14 #23 17 h ffffa0 h icr06 0000b6 h dtp/external interrupt ch.6/ch.7 #24 18 h ffff9c h no ?? #25 19 h ffff98 h icr07 0000b7 h no ?? #26 1a h ffff94 h no ?? #27 1b h ffff90 h icr08 0000b8 h no ?? #28 1c h ffff8c h no ?? #29 1d h ffff88 h icr09 0000b9 h ppg ch.0/ch.1 #30 1e h ffff84 h no ?? #31 1f h ffff80 h icr10 0000ba h ppg ch.2/ch.3 #32 20 h ffff7c h no ?? #33 21 h ffff78 h icr11 0000bb h no ?? #34 22 h ffff74 h no ?? #35 23 h ffff70 h icr12 0000bc h no ?? #36 24 h ffff6c h uart (send completed) ch.0/ch.1 13 #37 25 h ffff68 h icr13 0000bd h extended serial i/o 9 #38 26 h ffff64 h uart(reception completed) ch.0/ch.1 12 #39 27 h ffff60 h icr14 0000be h time-base timer #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delay interrupt output module #42 2a h ffff54 h low
MB90335 series 23 (continued) : available. ei 2 os stop function provided (the interrupt reques t flag is cleared by the interrupt clear signal. with a stop request). : available (the interrupt request flag is cleared by the interrupt clear signal). : available when any interrupt source sharing icr is not used. : unavailable *1 : if the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. *2 : ch.2 and ch.3 can be used in mini-host operation. notes : ? if the same interrupt control register (icr) has two interrupt factors and the use of the ei 2 os is permitted, the ei 2 os is activated when either of the factors is detected. as any interrupt other than the activation factor is masked while the ei 2 os is running, it is recommended that you should mask either of the interrupt requests when using the ei 2 os. ? the interrupt flag is cleared by the ei 2 os interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (icr). ? if a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the dmac interrupt clear signal. therefore, when you use either of two interrupt factors for the dmac function, another interrupt function is disabled. set the interrupt request permission bit to ? 0 ? in the appropriate resource, and take measures by software polling. content of usb in terruption factor * : end point 1and 2 can be used in mini-host operation. usb interrupt factor details usb function 1 end point0-in, endpoint 0-out usb function 2 end point 1-5 * usb function 3 susp, sof, brst, wkop, cohf usb function 4 spit usb mini-host1 dirq, chhirq, urirq, rwkirq usb mini-host2 sofirq, cmpirq
MB90335 series 24 peripheral resources 1. i/o port the i/o ports are used as general-purpose input/output ports (parallel i/o ports). MB90335 series model is provided with 6 ports (45 inputs) . the ports function as input/output pins for peripheral functions also. an i/o port, using port data register (pdr) , outputs the output data to i/o pin and input a signal input to i/o port. the port direction register (ddr) specifies direction of input/output of i/o pins on a bit-by-bit basis. the following table lists the i/o ports and the peripheral functions with which they share pins. port pin name pin name (peripheral) peripheral function that shares pin port 0 p00 to p07 ? port 1 p10 to p17 ? port 2 p20 to p23 ? p24 to p27 ppg0 to ppg3 8 /16-bit ppg timer 0, 1 port 4 p40, p41 tin0, tot0 16-bit reload timer p42 to p47 sin0, sot0, sck0, sin1, sot1, sck1 uart0, 1 port 5 p50 to p54 ? port 6 p60, p61 int0, int1 external interrupt p62 to p64 int2 to int4, sin, sot, sck external interrupt, serial i/o p65 int5, pwc externa l interrupt, pwc p66, p67 int6, int7, scl0, sda0 external interrupt, i 2 c
MB90335 series 25 ? register list (port data register) * : r/w access to i/o ports is a bit different in behavior from r/w access to memory as follows: ? input mode read : the level at the relevant pin is read. write : data is written to the output latch. ? output mode read : the data register latch value is read. write : data is output to the relevant pin. pdr0 initial value access address : 000000 h xxxxxxxx b r/w* pdr1 address : 000001 h xxxxxxxx b r/w* pdr2 address : 000002 h xxxxxxxx b r/w* pdr4 address : 000004 h xxxxxxxx b r/w* pdr5 address : 000005 h - - - xxxxx b r/w* pdr6 address : 000006 h xxxxxxxx b r/w* 7654 321 0 p06 p07 p05 p04 p03 p02 p01 p00 15 14 13 12 11 10 9 8 p16 p17 p15 p14 p13 p12 p11 p10 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 15 14 13 12 11 10 9 8 ? ?? p54 p53 p52 p51 p50 7654 321 0 p66 p65 p64 p63 p62 p61 p60 p67
MB90335 series 26 ? register list (port direction register) when each pin is serving as a port, the corresponding pin is controlled as follows: 0 : input mode 1 : output mode this bit becomes 0 after a reset. note : if these registers are accessed by a read modify wr ite instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to current input values of the pins. when switching a pin from input port to output port, therefore, write a desired value in the pdr first, then set the ddr to switch the pin for output. ? register list (port pull-up register) controls the pull-up re sistor in input mode. 0 : without pull-up resistor in input mode. 1 : with pull-up resistor in input mode. meaningless in output mode (without pull-up resistor) ./ the input/output register is decided by the setting of the direction register (ddr) . no pull-up resistor is used in stop mode (spl = 1). ddr0 initial value access address : 000010 h 00000000 b r/w ddr1 address : 000011 h 00000000 b r/w ddr2 address : 000012 h 00000000 b r/w ddr4 address : 000014 h 00000000 b r/w ddr5 address : 000015 h - - - 00000 b r/w ddr6 address : 000016 h 00000000 b r/w 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d 00 15 14 13 12 11 10 9 8 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 d26 d27 d25 d24 d23 d22 d21 d20 7654 321 0 d46 d47 d45 d44 d43 d42 d41 d40 15 14 13 12 11 10 9 8 ? ?? d54 d53 d52 d51 d50 7654 321 0 d66 d67 d65 d64 d63 d62 d61 d60 rdr0 initial value access address : 00001c h 00000000 b r/w rdr1 address : 00001d h 00000000 b r/w 7654 321 0 rd06 rd07 rd05 rd04 rd03 rd02 rd01 rd00 15 14 13 12 11 10 9 8 rd16 rd17 rd15 rd14 rd13 rd12 rd11 rd10
MB90335 series 27 ? register list (output pin register) controls open-drain output in output mode. 0 : serves as a standard output port in output mode. 1 : serves as an open-drain output port in output mode. meaningless in input mode. (output hi-z) / the input/output register is decided by the setting of the direction register (ddr) . ? block diagram of port 0 pin and port1 pin ? block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin odr4 initial value access address : 00001b h 00000000 b r/w 7654 321 0 od46 od47 od45 od44 od43 od42 od41 od40 pull-up resistor setting register (rdrx) port data register (pdrx) port direction register (ddrx) i/o decision circuit input buffer output buffer internal data bus pdrx read pdrx write port pin built-in pull-up resistor standby control (lpmcr : spl = ?1?) port data register (pdrx) port direction register (ddrx) i/o decision circuit input buffer output buffer internal data bus pdrx read pdrx write port pin standby contro l (lpmcr : spl = ?1?) resource output control signal resource output resource input
MB90335 series 28 2. time-base timer the time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock hclk). four differen t time intervals can be selected, for each of which an interrupt request can be generated. op erating clock signals are supplied to peripheral resources such as the oscillation stabilizati on wait timer and watchdog timer. ? interval time of time-base timer notes : ? hclk : oscillation clock frequency ? the parenthesized values assume an oscillator clock frequency of 6 mhz. ? clock cycles supplied from time-base timer notes : ? hclk : oscillation clock frequency ? the parenthesized va lues assume an oscillator clock frequency of 6 mhz. ? register list internal count clock cycle interval time 2/hclk (0.33 s) 2 12 /hclk (approx. 0.68 ms) 2 14 /hclk (approx. 2.7 ms) 2 16 /hclk (approx. 10.9 ms) 2 19 /hclk (approx. 87.4 ms) where to supply clock clock cycle main clock oscillation stabilization wait 2 13 /hclk (approx. 1.36 ms) 2 15 /hclk (approx. 5.46 ms) 2 17 /hclk (approx. 21.84 ms) watch dog timer 2 12 /hclk (approx. 0.68 ms) 2 14 /hclk (approx. 2.7 ms) 2 16 /hclk (approx. 10.9 ms) 2 19 /hclk (approx. 87.4 ms) time-base timer control register (tbtc) initial value address : 0000a9 h 1--00100 b ( ? )( ? ) ( r/w ) ( r/w ) ( w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( r/w ) resv ? tbie tbof tbr tbc1 tbc0
MB90335 series 29 ? block diagram actual interrupt request number of time-base timer is as follows: interrupt request number:#40 (28 h ) tbie tbof tbr resv ?? tbc1 tbc0 of of of of 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 to ppg timer time-base timer counter dividing hclk by 2 to watchdog timer ckscr : mcs = 1 0* counter clear control circuit interval timer selector tbof clear time-base timer control register (tbtc) time-base timer interrupt signal to clock controller oscillation stabilizing wait time selector tbof set ? : unused of : overflow hclk : oscillation clock * : switching the machine clock from main clock to pll clock power-on reset stop mode start
MB90335 series 30 3. watchdog timer the watchdog timer is timer counter provided for measure of program runaway. it is a 2-bit counter operating with an output of the timebase timer or watch timer as the count clock and resets the cpu when the counter is not cleared for a preset period of time after start. ? interval time of watchdog timer notes : ? the maximum and minimum time intervals for the watchdog timer depend on the counter clear timing. ? the watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer. ? interval time of watchdog timer is longer than the set time during the following conditions. - when clearing the timeba se timer during operation on oscillation (hclk) ? event that stop the watchdog timer ? stop due to a power-on reset ? watchdog reset ? clear factor of watchdog timer ? external reset input by rst pin ? writing ?0? to the software reset bit ? writing ?0? to the watchdog control bit (second and subsequent times) ? transition to sleep mode (clearing th e watchdog timer to suspend counting) ? transition to time-base timer mode (clearing the watchdog timer to suspend counting) ? transition to stop mode (clearing the watchdog timer to suspend counting) ? register list hclk: oscillation clock (6 mhz) min max clock cycle approx. 2.39 ms approx. 3.07 ms 2 14 2 11 / hclk approx. 9.56 ms approx. 12.29 ms 2 16 2 13 / hclk approx. 38.23 ms approx. 49.15 ms 2 18 2 15 / hclk approx. 305.83 ms approx. 393.22 ms 2 21 2 18 / hclk watchdog timer control register (wdtc) initial value address : 0000a8 h x - xxx111 b ( ? ) ( r ) ( r ) ( r ) ( w ) ( w ) ( w ) 7654 3210 ( r ) ponr wrst erst srst wte wt1 wt0 ?
MB90335 series 31 ? block diagram ponr ? wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 clr clr 2 4 watchdog timer control register (wdtc) watchdog timer time-base timer mode start sleep mode start counter clear control circuit count clock selector 2-bit counter watchdog timer reset generation circuit to internal reset generation circuit clr and start time-base timer counter dividing hclk by 2 hclk: oscillation clock clear stop mode start
MB90335 series 32 4. 16-bit reload timer the 16-bit reload timer has the internal clock mode to be decrement in synchronization with 3 different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. either can be selected. this timer defines when the count value changes from 0000 h to ffff h as an underflow. the timer therefore causes an underflow when the count reaches [reload register setting +1]. either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. the interrupt can be generated at the counter underflow occurrence so as to correspond to the dtc. ? register list ? timer control status register timer control status register (upper) (tmcsr0) timer control status register (lower) (tmcsr0) ? 16-bit timer register/16-bit reload register tmr0/tmrlr0 (upper) tmr0/tmrlr0 (lower) initial value address : 000063 h xxxx0000 b initial value address : 000062 h 00000000 b initial value address : 000065 h xxxxxxxx b initial value address : 000064 h xxxxxxxx b ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ??? csl1 csl0 mod2 mod1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 oute ( r/w ) mod0 outl reld inte uf cnte trg ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 d14 ( r/w ) d15 d13 d12 d11 d10 d09 d08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 d06 ( r/w ) d07 d05 d04 d03 d02 d01 d00
MB90335 series 33 ? block diagram tmrlr0 tmr0 clk tin0 uf en tot0 clk 3 3 2 ???? csl1 csl0 mod2 mod1 mod0 oute outl reld uf inte cnte trg *2 internal data bus 16-bit reload register 16-bit timer register reload signal reload control circuit wait signal output control circuit output signal generation circuit pin valid clock decision circuit clock selector operating control circuit select signal external clock internal clock input control circuit pin prescaler count clock generation circuit gate input timer control status register (tmcsr0) interrupt request output #23 (17 h )* 1 select function clear trigger machine clock *1 : interrupt number *2 : underflow
MB90335 series 34 5. multifunction timer the multifunction timer can be used for waveform output, input pulse width measurement, and external clock cycle measurement. ? configuration of a multi-functional timer ? 8/16-bit ppg timer (8-bit : 4 channels, 16-bit : 2 channels) 8/16-bit ppg timer consists of a 8-bit down counter (pcnt) , ppg operation mode control register (ppgc0 to ppgc3) , ppg output control register (ppg01, ppg23) and ppg reload register (prll0 to prll3, prlh0 to prlh3) . when used as an 8/16-bit reload timer, the ppg timer se rves as an event timer. it can also output pulses of an arbitrary duty ratio at an arbitrary frequency. 8-bit ppg mode each channel operates as an independent 8-bit ppg. 8-bit prescaler + 8-bit ppg mode operates as an arbitrary-cycle 8-bit ppg with ch.0 (ch.2) operating as an 8-bit prescaler and ch.2 (ch.3) counted by the borrow output of ch.0 (ch.2). 16-bit ppg mode operates as a 16-bit ppg with ch.0 (ch.2) and ch.1 (ch.3) connected. ppg operation the ppg timer outputs pulses of an arbitrary duty ratio (the ratio between the high and low level periods of pulse waveform) at an arbitrary frequency. can also be used as a d/a converter by an external circuit. 8/16-bit ppg timer 16-bit pwc timer 8-bit 4 channels (16-bit 2 channels) 1 channel
MB90335 series 35 ? register list ppg operation mode control register (ppgc1/ppgc3) (ppgc0/ppgc2) ppg output control register (ppg01/ppg23) ppg reload register (prlh0 to prlh3) (prll0 to prll3) address : 000047 h 000049 h initial value 0x000001 b address : 000046 h 000048 h initial value 0x000xx1 b address : 00004c h 00004e h initial value 000000xx b address : 007901 h 007903 h 007905 h 007907 h initial value xxxxxxxx b address : 007900 h 007902 h 007904 h 007906 h initial value xxxxxxxx b 15 14 13 12 11 10 9 8 ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ? pen1 pe10 pie1 puf1 md1 md0 reserved 7654 3210 ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ? pen0 pe0o pie0 puf0 ?? reserved 7654 321 0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) pcs1 pcs2 pcs0 pcm2 pcm1 pcm0 reserved reserved 15 14 13 12 11 10 9 8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) d14 d15 d13 d12 d11 d10 d09 d08 7654 321 0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) d06 d07 d05 d04 d03 d02 d01 d00
MB90335 series 36 ? 8/16-bit ppg ch.0/ch.2 block diagram ppg0/ppg2 pen0 irq pie0 puf0 prll prlhb prll s rq pcnt (down counter) peripheral clock 16 ppg0/ppg2 output latch count clock selector timebase counter output main clock 512 ch.1/ch.3 borrow l/h selector ppgc0 (operation mode control) * : interrupt number to interrupt #30 (1e h )* #32 (20 h )* l/h selector ppg0/ppg2 output enable peripheral clock 8 peripheral clock 4 peripheral clock 2 peripheral clock a/d converter l data bus h data bus
MB90335 series 37 ? 8/16-bit ppg ch.1/ch.3 block diagram ppg1/ppg3 pen1 irq pie1 puf1 prll prlhb prll s rq pcnt (down counter) peripheral clock 16 ppg1/ppg3 output latch count clock selector timebase counter output main clock 512 l/h selector ppgc1 (operation mode control) * : interrupt number to interrupt #30 (1e h )* #32 (20 h )* l/h selector ppg1/ppg3 output enable peripheral clock 8 peripheral clock 4 peripheral clock 2 peripheral clock l data bus h data bus
MB90335 series 38 ? pwc timer the pwc timer is a 16-bit multi-function up-count ti mer capable of measuring the input signal pulse width. ? register list pwc control status register (pwcsr) pwc data buffer register (pwcr) pwc ratio of dividing frequency control register (divr) initial value address : 00005d h 0000000x b initial value address : 00005c h 00000000 b initial value address : 00005f h 00000000 b initial value address : 00005e h 00000000 b initial value address : 000060 h ------ 00 b ( r/w ) ( r ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r/w ) 15 14 13 12 11 10 9 8 stop ( r/w ) strt edir edie ovir ovie err reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3210 cks0 ( r/w ) cks1 pis1 pis0 s/c mod2 mod1 mod0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 d14 ( r/w ) d15 d13 d12 d11 d10 d9 d8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ????? div1 div0
MB90335 series 39 ? block diagram err pwcr 16 16 ck s 1/ck s 0 15 err ck s 0/ck s 1 pi s 0/pi s 1 pwc s r divr 16- b it u p-co u nt timer control circ u it 2 2 2 2 3 pwc 8 - b it divider pwcr read error detection reload data transfer over- flow clock internal clock (machine clock/4) clock divider timer clear count enable divider clear flag set etc... control bit output start edge selection measurement termination edge end edge selection edge detection divider on/off measurement starting edge overflow interrupt request divide ratio select f 2 mc-16 bus measurement termination interrupt request input waveform comparator pin
MB90335 series 40 6. uart uart is a general purpose serial communication interf ace for synchronous or asynchronous (start-stop syn- chronization) communications with external devices. it supports bi-directional communication (normal mo de) and master/slave communication (multi-processor mode: supported on master side only). an interrupt can be generated upon completion of reception, detection of a reception error, or upon completion of transmission. ei 2 os is supported. ? uart functions uart, or a generic serial data communication interface that sends and receives serial data to and from other cpu and peripherals, has the functions listed in following. note : in clock synchronous transfer mode, the uart transfers only data with no start or stop bit added. ? uart operation modes ? : setting disabled *1 : + 1 is an address/data setting bit (a/d) which is used for communication control. *2 : only one bit can be detected as a stop bit at reception. operation mode data length synchronization stop bit length without parity with parity 0 normal mode 7-bit or 8-bit asynchronous 1-bit or 2-bit * 2 1 multi processor mode 8-bit + 1 * 1 ? asynchronous 2 normal mode 1 to 8-bit ? synchronous no function data buffer full-duplex double-buffered transmission mode clock synchronous (without start/stop bit) clock asynchronous (s tart-stop synchronous) baud rate special-purpose baud-rate generator it is optional from 8 kinds. baud rate by external clock (clock of sck0/sck1 terminal input) data length 8-bit or 7-bit (in the asynchronous normal mode only) 1 to 8 bits (in the synchronous mode only) signaling system non return to zero (nrz) system reception error detection framing error overrun error parity error (not supported in operation mode 1) interrupt request receive interrupt (reception completed, reception error detected) transmission interrupt (transmission completed) both the transmission and reception support ei 2 os. master/slave type communication function (multi processor mode) capable of 1 (master) to n (slaves) communication (available just as master)
MB90335 series 41 ? register list serial mode register (smr0, smr1) serial control register (scr0, scr1) serial input/output data register (sidr0, sidr1 / sodr0, sodr1) serial status register (ssr0, ssr1) uart prescaler reload register (utrlr0, utrlr1) uart prescaler control register (utcr0, utcr1) 000020 h 000026 h initial value address : 00100000 b 000021 h 000027 h initial value address : 00000100 b 000022 h 000028 h initial value address : xxxxxxxx b 000023 h 000029 h initial value address : 00001000 b 000024 h 00002a h initial value address : 00000000 b 000025 h 00002b h initial value address : 0000 - 000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 md0 ( r/w ) md1 sckl m2l2 m2l1 scke soe m2l0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 p ( r/w ) pen sbl cl a/d rec rxe txe ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( r ) ( r ) ( r ) ( r ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ore ( r ) pe fre rdrf tdre bds rie tie ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0 ( r/w ) ( r/w ) ( r/w ) ( ? ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 srst ( r/w ) md cks ? d10 d9 d8 reserved
MB90335 series 42 ? block diagram md1 md0 sckl m2l2 m2l1 m2l0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre bds rie tie sidr0, sidr1 sck0, sck1 sot0, sot1 #39 (27 h ) * #37 (25 h ) * sin0, sin1 sodr0, sodr1 smr0 , smr1 scr0 , scr1 ssr0 , ssr1 reception complete control bus special-purpose baud-rate generator (uart prescaler control register utcr0, utcr1) (uart prescaler reload resister utrlr0, utrlr1) clock selector receive status decision circuit reception error occurrence signal for ei 2 os (to cpu) reception clock reception control circuit start bit detection circuit reception bit counter reception parity counter shift register for reception internal data bus transmission clock reception interrupt signal transmission control circuit transmission start circuit transmission bit counter transmission parity counter shift register for transmission start transmission * : interrupt number send interrupt signal pin pin pin
MB90335 series 43 7. extended i/o serial interface the extended i/o serial interface is a serial i/o interface that can transfer data through the adoption of 8-bit 1 channel configured clock synchronization scheme. lsb-fi rst or msb-first transfer mode can be selected for data transfer. there are 2 serial i/o operation modes available: internal shift clock mode : transfer data in synchronization with the internal clock. external shift clock mode : transfer data in synchronization with the clock supplied via the external pin (sck). by manipulating the general-purpose port sharing the external pin (sck) in this mode, data can also be transferred by a cpu instruction. ? register list serial mode control status register (smcs) serial data register (sdr) communication prescaler control register (sdcr) initial value address : 000059 h 00000010 b initial value address : 000058 h xxxx0000 b initial value address : 00005a h xxxxxxxx b initial value address : 00005b h 0xxx0000 b 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt ( r/w ) ( r ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ? ??? mode bds soe scoe ( ? ) ( ? ) ( ? ) ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 d7 d5 d4 d3 d2 d1 d0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( r/w ) md ?? div3 div2 div1 div0
MB90335 series 44 ? block diagram sin sot sck smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 soe scoe (msb first) d0 to d7 d7 to d0 (lsb first) sdr (serial data register) internal clock internal data bus transfer direct ion selection read write control circuit shift clock counter interrupt request internal data bus initial value
MB90335 series 45 8. i 2 c interface the i 2 c interface is a serial i/o port supporting the inter ic bus. it serves as a master/slave device on the i 2 c bus and has the following features. master/slave sending and receiving arbitration function clock synchronization function slave address and general call address detection function detecting transmitting direction function start condition repeated generation and detection function bus error detection function ? register list i 2 c bus status register (ibsr0) i 2 c bus control register (ibcr0) i 2 c bus clock control register (iccr0) i 2 c bus address register (iadr0) i 2 c bus data register (idar0) initial value address : 000070 h 00000000 b initial value address : 000071 h 00000000 b initial value address : 000072 h xx0xxxxx b initial value address : 000073 h xxxxxxxx b initial value address : 000074 h xxxxxxxx b ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 rsc ( r ) bb al lrb trx aas gca fbt ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 beie ( r/w ) ber scc mss ack gcaa inte int ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ? en cs4 cs3 cs2 cs1 cs0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 a6 ( ? ) ? a5 a4 a3 a2 a1 a0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 d6 ( r/w ) d7 d5 d4 d3 d2 d1 d0
MB90335 series 46 ? block diagram iccr en iccr ib s r bb r s c lrb l as t bit trx fbt al ibcr ber beie inte int ibcr s cc m ss ack gcaa ib s r idar iadr aa s gca c s 4 c s3 c s 2 c s 1 c s 0 24 8 16 12 8 256 3 264 56 7 8 s ync fir s t byte f 2 mc-16 bus irq s cl0 s da0 i 2 c enable clock divide 2 clock selector 2 bus busy repeat start send/receive start stop condition generation arbitration lost detection interrupt request start master ack enable gc-ack enable slave slave address compare end error shift clock edge change timing start stop condition detection generating shift clock clock divide 1 clock selector 1 peripheral clock global call
MB90335 series 47 9. usb function the usb function is an interface supporting the u sb (universal serial bus) communications protocol. feature of usb function conform to usb 2.0 full speed full speed (12 mbps) is supported. the device status is auto-answer. bit stripping, bit stuffing, and automatic generation and check of crc5 and crc16. toggle check by data synchronization bit. automatic response to all standard commands except get/setdescriptor and synchframe commands (these three commands can be processed the same way as the class vendor commands). the class vendor commands can be received as data and responded via firmware. supports up to maximum six endpoints (endpoint0 is fixed to control transfer). two transfer data buffers integrated for each end point (one in buffer and one out buffer for end point 0). supports automatic transfer mode for transfer data via dma (except buffers for endpoint0). ? register list (continued) udc control register (udcc) ep0 control register (ep0c) ep1 control register (ep1c) initial value address : 0000d0 h 10100000 b initial value address : 0000d1 h 00000000 b initial value address : 0000d2 h 01000000 b initial value address : 0000d3 h xxxx0000 b initial value address : 0000d4 h 00000000 b initial value address : 0000d5 h 01100001 b ( r/w ) ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ( r/w ) 7654 3 21 0 re s um ( r/w ) r s t hcon u s tp rfbk pwc reserved reserved ( ? )( ? )( ? )( ? )( ? )( ? )( ? ) 15 14 13 12 11 10 9 8 ( ? ) reserved reserved reserved reserved reserved reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks0 ( ? ) pks0 pks0 pks0 pks0 pks0 pks0 reserved ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 ? ( ? ) ??? stal reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks1 ( r/w ) pks1 pks1 pks1 pks1 pks1 pks1 pks1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 type ( r/w ) epen type dir dmae nule stal pks1
MB90335 series 48 (continued) ep2/3/4/5 control register (ep2c to ep5c) time stamp register (tmsp) udc status register (udcs) udc interrupt enable register (udcie) ep0i status register (ep0is) initial value address : 0000d6 h 0000d8 h 01000000 b 0000da h 0000dc h initial value address : 0000d7 h 0000d9 h 01100000 b 0000db h 0000dd h initial value address : 0000de h 00000000 b initial value address : 0000df h xxxxx000 b initial value address : 0000e0 h xx000000 b initial value address : 0000e1 h 00000000 b initial value address : 0000e2 h xxxxxxxx b initial value address : 0000e3 h 10xxx1xx b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 pks2 5 ( r/w ) pks2 5 pks2 5 pks2 5 pks2 5 pks2 5 pks2 5 reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 type ( r/w ) epen type dir dmae nule stal reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 tmsp ( r ) tmsp tmsp tmsp tmsp tmsp tmsp tmsp ( ? )( ? )( ? )( ? ) ( r ) ( r ) ( r ) 15 14 13 12 11 10 9 8 ? ( ? ) ? ??? tmsp tmsp tmsp ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ? susp sof brst wkup setp conf ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r/w ) 15 14 13 12 11 10 9 8 ( ? ) suspie sofie brstie wkupie confn confie reserved reserved ( ? )( ? )( ? )( ? )( ? )( ? )( ? ) 76543210 ? ( ? ) ?????? ? ( r/w ) ( ? )( ? )( ? ) ( r/w ) ( ? )( ? ) 15 14 13 12 11 10 9 8 drqiie ( r/w ) bfini ??? drqi ??
MB90335 series 49 (continued) ep0o status register (ep0os) ep1 status register (ep1s) ep2/3/4/5 status regist er (ep2s to ep5s) ep0/1/2/3/4/5 data register (ep0dt to ep5dt) initial value address : 0000e4 h 0xxxxxxx b initial value address : 0000e5 h 100xx000 b initial value address : 0000e6 h xxxxxxxx b initial value address : 0000e7 h 1000000x b initial value address : 0000e8 h 0000ea h 0xxxxxxx b 0000ec h 0000ee h initial value address : 0000e9 h 0000eb h 10000000 b 0000ed h 0000ef h 0000f0 h 0000f2 h initial value address : 0000f4 h 0000f6 h xxxxxxxx b 0000f8 h 0000fa h 0000f1 h 0000f3 h initial value address : 0000f5 h 0000f7 h xxxxxxxx b 0000f9 h 0000fb h ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 size ( ? ) size size size size size size reserved ( r/w ) ( r/w ) ( ? )( ? ) ( r/w ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 drqoie ( r/w ) bfini spkie ?? drqo spk reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 size ( r ) size size size size size size size ( r/w ) ( r/w ) ( ? ) ( r ) ( r/w ) ( r/w ) ( r ) 15 14 13 12 11 10 9 8 drqie ( r/w ) bfini spkie busy drq spk size reserved ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) 76543210 size ( ? ) size size size size size size reserved ( r/w ) ( r/w ) ( ? ) ( r ) ( r/w ) ( r/w ) ( ? ) 15 14 13 12 11 10 9 8 drqie ( r/w ) bfini spkie busy drq spk reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 bfdt ( r/w ) bfdt bfdt bfdt bfdt bfdt bfdt bfdt ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 bfdt ( r/w ) bfdt bfdt bfdt bfdt bfdt bfdt bfdt
MB90335 series 50 10. usb mini - host usb mini-host provides minimal host operations required and is a function that enables data to be transferred to and from device without pc intervention. ? feature of usb mini - host automatic detection of low speed/full speed transfer low speed/full speed transfer support automatic detection of connection and cutting device reset sending function support to usb-bus support of in/out/setup/sof token in-token handshake packet automatic transmission (excluding stall) handshake packet automatic detection at out-token supports a maximum packet length of 256 bytes error (crc erro r/toggle error/time-o ut) various supports wake-up function support ? differences between the usb host and usb mini-host : supported : not supported host mini-host hub support transfer bulk transfer control transfer interrupt transfer iso transfer transfer speed low speed full speed pre packet support sof packet support error crc error toggle error time-out maximum packet < receive data detection of connection and cutting of device transfer speed detection
MB90335 series 51 ? register list (continued) host control register 0 (hcnt0) host control register 1 (hcnt1) host interruption register (hirq) host error status register (herr) host state status register (hstate) sof interruption frame comparison register (hfcomp) retry timer setting register (hrtimer) initial value address : 0000c0 h 00000000 b initial value address : 0000c1 h 00000001 b initial value address : 0000c2 h 00000000 b initial value address : 0000c3 h 00000011 b initial value address : 0000c4 h xx010010 b initial value address : 0000c5 h 00000000 b initial value address : 0000c6 h 00000000 b initial value address : 0000c7 h 00000000 b initial value address : 0000c8 h xxxxxx00 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 urire ( r/w ) rwkire cmpire cnnire dire sofire urst host ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ( r/w ) sofstep cancel retry reserved reserved reserved reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ( r/w ) tcan rwkirq urirq cmpirq cnnirq dirq sofirq reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rerr ( r/w ) lstsof tout crc tgerr stuff hs hs ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r ) ( r ) 76543210 ? ( ? ) ? alive clksel sofbusy susp tmode cstat ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ( r/w ) frame comp frame comp frame comp frame comp frame comp frame comp frame comp frame comp ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 rtimer0 ( r/w ) rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 rtimer0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rtimer1 ( r/w ) rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 rtimer1 ( ? )( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) 76543210 ? ( ? ) ????? rtimer2 rtimer2
MB90335 series 52 (continued) host address register (hadr) eof setting register (heof) frame setting register (hframe) host token end point register (htoken) initial value address : 0000c9 h x0000000 b initial value address : 0000ca h 00000000 b initial value address : 0000cb h xx000000 b initial value address : 0000cc h 00000000 b initial value address : 0000cd h xxxxx000 b initial value address : 0000ce h 00000000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 address ( ? ) ? addressaddressaddressaddressaddressaddress ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 eof0 ( r/w ) eof0 eof0 eof0 eof0 eof0 eof0 eof0 ( ? ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ? eof1 eof1 eof1 eof1 eof1 eof1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 frame0 ( r/w ) frame0 frame0 frame0 frame0 frame0 frame0 frame0 ( ? )( ? )( ? )( ? ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ? ( ? ) ? ??? frame1 frame1 frame1 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 tknen ( r/w ) tggl tknen tknen endpt endpt endpt endpt
MB90335 series 53 11. dtp/external interrupt circuit dtp (data transfer peripheral)/external interrupt circuit detects the interrupt request input from the external interrupt input terminal int7 to int0, and outputs the interrupt request. ? dtp/external interrupt circuit function the dtp/external interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (int7 to int0). if cpu accept the interrupt request, and if the extended intelligent i/o service (ei 2 os) is enabled, branches to the interrupt handling routine after completing the automatic data transfer (dtp function) performed by ei 2 os. and if ei 2 os is disabled, it branches to the interrupt handling routine without activating the automatic data transfer (dtp function) performed by ei 2 os. ? feature of dtp/external interrupt circuit ? register list external interrupt dtp function input pin 8 channels (p60/int0, p61/int1, p62/int2/sin, p63/int3/sot, p64/int4/sck, p65/int5/pwc, p66/int6/scl0, p67/int7/sda0) interrupt source the detection level or the type of the edge for each terminals can be set in the request level setting register (elvr) input of ?h? level/ ?l? le vel/rising edge /falling edge. interrupt number #18 (12 h ) , #20 (14 h ) , #22 (16 h ) , #24 (18 h ) interrupt control enabling/prohibit the interrupt request output using the dtp/interrupt enable register (enir) interrupt flag holding the interrupt source using the dtp/interrupt cause register (eirr) process setting prohibit ei 2 os (icr: ise=?0?) enable ei 2 os (icr: ise=?1?) process branched to the interrupt handling routine after an automatic data transfer by ei 2 os, branched to the interrupt handling routine dtp/interrupt enable register (enir) dtp/interrupt source register (eirr) request level setting register (elvr) initial value address : 00003c h 00000000 b initial value address : 00003d h 00000000 b initial value address : 00003e h 00000000 b initial value address : 00003f h 00000000 b 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) er6 er7 er5 er4 er3 er2 er1 er0 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) la3 lb3 lb2 la2 lb1 la1 lb0 la0 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) la7 lb7 lb6 la6 lb5 la5 lb4 la4
MB90335 series 54 ? block diagram lb7 er7 er6 er5 er4 er3 er2 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 p60/int0 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 p61/int1 p62/int2/ sin p63/int3/ sot #18(12 h ) * #20(14 h ) * #22(16 h ) * #24(18 h ) * 22222222 p64/int4/ sck p65/int5/ pwc p66/int6/ scl0 p67/int7/ sda0 request level settin g register (elvr) pin pin pin pin selector selector selector selector selector selector selector selector pin pin pin pin interrupt request signal internal data bus dtp/interrupt source register (eirr) dtp/interrupt enable register (enir) * : interrupt number dtp/external interrupt input detection circuit
MB90335 series 55 12. interrupt controller the interrupt control register is located inside the interrupt controller, it exists for every i/o having an interrupt function. this register has the following functions. setting of the interrupt levels of relevant peripheral ? register list note : do not access interrupt control registers using any read modify write instruction because it causes a malfunction. ? block diagram interrupt control register (icr01 , icr03, icr05, icr07, icr09, icr11, icr13, icr15) interrupt control register (icr00, icr02, icr04, icr06, icr08, icr10, icr12, icr14) initial value address : icr01 : 0000b1 h icr03 : 0000b3 h icr05 : 0000b5 h icr07 : 0000b7 h icr09 : 0000b9 h icr11 : 0000bb h icr13 : 0000bd h icr15 : 0000bf h 00000111 b initial value address : icr00 : 0000b0 h icr02 : 0000b2 h icr04 : 0000b4 h icr06 : 0000b6 h icr08 : 0000b8 h icr10 : 0000ba h icr12 : 0000bc h icr14 : 0000be h 00000111 b ( w ) ( w ) ( w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 ics2 ( w ) ics3 ics1 ics0 ise il2 il1 il0 ( w ) ( w ) ( w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ics2 ( w ) ics3 ics1 ics0 ise il2 il1 il0 il2 il1 il0 32 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 determine priority of interrupt interrupt request (peripheral resource) (cpu) interrupt level f 2 mc - 16lx bus
MB90335 series 56 13. dmac dmac is simple dma with the function equal with ei 2 os. it has 16 channels dma transfer channels with the following features. performs automatic data transfer between the peripheral resource (i/o) and memory the program execution of cpu stops in the dma startup capable of selecting whether to increment the transfer source and destination addresses dma transfer is controlled by the dma enable register, dma stop status register, dma status register and descriptor a stop request is available for stopping dma transfer from the resource upon completion of dma transfer, the flag bit corresponding to the transfer completed channel in the dma status register is set and a termination interrupt is output to the transfer controller. ? register list (continued) dma enable register upper (derh) dma enable register lower (derl) dma stop status register (dssr) dma status register upper (dsrh) dma status register lower (dsrl) dma descriptor channel specification register (dcsr) * : the dssr is lower when the stp bit of dcsr in the dssr is ?0?. the dssr is upper when the stp bi t of dcsr in the dssr is ?1?. initial value address : 0000ad h 00000000 b initial value address : 0000ac h 00000000 b initial value address : 0000a4 h 00000000 b * initial value address : 00009d h 00000000 b initial value address : 00009c h 00000000 b initial value address : 00009b h 00000000 b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 en14 ( r/w ) en15 en13 en12 en11 en10 en9 en8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 en6 ( r/w ) en7 en5 en4 en3 en2 en1 en0 76543210 stp6 stp14 stp7 stp15 stp5 stp13 stp4 stp12 stp3 stp11 stp2 stp10 stp1 stp9 stp0 stp8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 dte14 dte15 dte13 dte12 dte11 dte10 dte9 dte8 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dte6 ( r/w ) dte7 dte5 dte4 dte3 dte2 dte1 dte0 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 ( r/w ) stp dcsr3 dcsr2 dcsr1 dcsr0 reserved reserved reserved
MB90335 series 57 (continued) dma buffer address point er lower 8 bit (dbapl) dma buffer address point er middle 8 bit (dbapm) dma buffer address pointer upper 8 bit (dbaph) dma control register (dmacs) dma i/o register address pointer lower 8 bit (dioal) dma i/o register address pointer upper 8 bit (dioah) dma data counter lower 8 bit (ddctl) dma data counter upper 8 bit (ddcth) note : the above register is switched for each channel depending on the dcsr. initial value address : 007920 h xxxxxxxx b initial value address : 007921 h xxxxxxxx b initial value address : 007922 h xxxxxxxx b initial value address : 007923 h xxxxxxxx b initial value address : 007924 h xxxxxxxx b initial value address : 007925 h xxxxxxxx b initial value address : 007926 h xxxxxxxx b initial value address : 007927 h xxxxxxxx b ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dbapl ( r/w ) dbapl dbapl dbapl dbapl dbapl dbapl dbapl 15 14 13 12 11 10 9 8 dbapm dbapm dbapm dbapm dbapm dbapm dbapm dbapm ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 dbaph dbaph dbaph dbaph dbaph dbaph dbaph dbaph ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 rdy1 rdy2 bytel if bw bf dir se ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 a06 ( r/w ) a07 a05 a04 a03 a02 a01 a00 15 14 13 12 11 10 9 8 a14 a15 a13 a12 a11 a10 a09 a08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 b06 b07 b05 b04 b03 b02 b01 b00 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 b14 b15 b13 b12 b11 b10 b09 b08 ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w )
MB90335 series 58 14. address matching detection function when the address is equal to the value set in the address detection register, the instruction code to be read into the cpu is forcibly replaced wit h the int9 instruction code (01 h ). as a result, the cpu executes the int9 instruction when executing the set instruction. by performing processing by the int#9 interrupt routine, the program patch function is enabled. 2 address detection registers are provided, for each of which there is an interrupt enable bit. when the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the cpu is forcibly replaced with the int9 instruction code. ? register list ? program address detect register 0 (padr0) ? program address detect register 1 (padr1) ? program address detect control status register (pacsr) r/w : readable and writable x : undefined padr0 (lower) initial value address : 001ff0 h xxxxxxxx b padr0 (middle) initial value address : 001ff1 h xxxxxxxx b padr0 (upper) initial value address : 001ff2 h xxxxxxxx b padr1 (lower) initial value address : 001ff3 h xxxxxxxx b padr1 (middle) initial value address : 001ff4 h xxxxxxxx b padr1 (upper) initial value address : 001ff5 h xxxxxxxx b pacsr initial value address : 00009e h 00000000 b (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 76543 210 (r/w) ad1e ad0e reserved reserved reserved reserved reserved reserved
MB90335 series 59 15. delay interrupt generator module the delay interrupt generation module is a module that generates interrupts for switching tasks. a hardware interrupt can be generated by software. ? delay interrupt generator module function ? block diagram function and control interrupt source ? setting the r0 bit in the delayed interrupt request generation/release register to 1 (dirr: r0 = 1) generates a delayed interrupt request. ? setting the r0 bit in the delayed interrupt request generation/release register to 0 (dirr: r0 = 0) cancels the delayed interrupt request. interrupt control no setting of permission register is provided. interrupt flag set in bit r0 of the delayed interrupt request generation /clear register (dirr : r0) ei 2 os support not ready for exte nded intelligent i/o service (ei 2 os). ??????? r0 internal data bus delayed interrupt source/release register (dirr) s interrupt request r latch ? : undefined bit interrupt request signal
MB90335 series 60 16. rom mirroring function selection module the rom mirror function select module can make a setting so that rom data located in bank ff can be read by accessing bank 00. ? rom mirroring function selection module function ? block diagram description mirror setting address ffffff h to ff8000 h in the ff bank can be read through 00ffff h to 008000 h in the 00 bank. interrupt source none ei 2 os support not ready for extended intelligent i/o service (ei 2 os). ?????? mi rom ff ba nk 00 ba nk internal data bus rom mirror function selection register (romm) address data address area re- served
MB90335 series 61 17. low power consumption (standby) mode the f 2 mc-16lx can be set to save power consumption by selecting and setting the low power consumption mode. ? cpu operation mode and functional description ? register list cpu operating clock operation mode description pll clock normal run the cpu and peripheral resources operate at the clock frequency obtained by pll multiplication of oscilla tor clock (hcl k) frequency. sleep only peripheral resources operate at the clock frequency obtained by pll multiplication of the oscilla tor clock (hclk) frequency. time-base timer only the time-base timer operates at the clock frequency obtained by pll multiplication of the oscilla tor clock (hclk) frequency. stop the cpu and peripheral re sources are suspended with the oscillator clock stopped. main clock normal run the cpu and peripheral resources operate at the clock frequency obtained by dividing the oscillator clo ck (hclk) frequency by two. sleep only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (hclk) frequency by two. time-base timer only the time-base timer operates at the clock frequency obtained by dividing the oscillator clock (hclk) frequency by two. stop the cpu and peripheral re sources are suspended with the oscillator clock stopped. cpu intermittent operation mode normal run the halved or pll-multip lied oscillator clock (hclk) frequency is used for operation while being decimated in a certain period. low power consumption mode control register (lpmcr) initial value address : 0000a0 h 00011000 b ( w ) ( r/w ) ( w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 7654 3 210 s lp ( w ) s tp s pl r s t tmd cg1 cg0 reserved
MB90335 series 62 18. clock the clock generator controls the internal clock as the operating clock for the cpu and peripheral resources. the internal clock is referred to as machine clock whose on e cycle is defined as machine cycle. the clock based on source oscillation is referred to as oscillator clock while the clock base d on internal pll oscillation as pll clock. ? register list clock selection register (ckscr) initial value address : 0000a1 h 11111100 b ( r ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 8 mcm ( r ) scm ws1 ws0 scs mcs cs1 cs0
MB90335 series 63 19. 512 kbits flash memory the description that follows applies to the flash memory built in the mb90f337; it is not applicable to evaluation rom or masked rom. the method of data write/erase to flash memory is following three types. ? parallel writer ? serial dedicated writer ? write/erase by executing program description of 512 kbits flash memory 512 kbits flash memory is located in ff h bank in the cpu memory map. function of flash memory interface circuit enables read and program access from cpu. write/erase to flash interface is executed by instruction from cpu via flash memory interface, so rewrite of program and data is carried on in the mounting state effectively. data can be reprogrammed not only by program execution in existing ram but by program execution in flash memory by dual operation. also, erase/write and read in the different bank (upper bank/lower bank) is executed simultaneously. features of 512 kbits flash memory ? sector configuration : 64 kwords 8 bits/32 words 16 bits (4 k 4 + 16 k 2 + 4 k 4) ? simultaneous execution of erase/write and read by 2-bank configuration ? automatic program algorithm (embedded algorithm tm *) ? built-in deletion pause/deletion resume function ? detection of programming/erasure comple tion using data polling and the toggle bit ? at least 10000 times guaranteed ? minimum flash read cycle time : 2 machine cycles * : embedded algorithm tm is a trade mark of advanced micro devices inc. note : the read function of manufacture code and device code is not including. also, these code is not accessed by the command. ? flash write/erase ? flash memory can not execute write/erase and read by the same bank simultaneously. ? data can be programmed/deleted into and erased from flash memory by executing either the program residing in the flash memory or the one copied to ram from the flash memory.
MB90335 series 64 ? sector configuration of flash memory s a0 (4 k b yte s ) s a1 (4 k b yte s ) s a2 (4 k b yte s ) s a 3 (4 k b yte s ) ff0000 h ff0fff h ff1000 h ff1fff h ff2000 h ff2fff h 70000 h 70fff h 71000 h 71fff h 72000 h 72fff h s a4 (16 k b yte s ) s a5 (16 k b yte s ) s a6 (4 k b yte s ) ff 3 000 h ff 3 fff h ff4000 h ff7fff h ff 8 000 h ffbfff h ffc000 h ffcfff h 7 3 000 h 7 3 fff h 74000 h 77fff h 7 8 000 h 7bfff h 7c000 h 7cfff h s a7 (4 k b yte s ) s a 8 (4 k b yte s ) s a9 (4k b yte s ) ffd000 h ffdfff h ffe000 h ffefff h fff000 h ffffff h 7d000 h 7dfff h 7e000 h 7efff h 7f000 h 7ffff h lower b a nk upper b a nk flash memory cpu address writer address * * : flash memory writer address indicates the address equivalent to the cpu address when data is written to the flash memory using a parallel writer. programming and erasing by the general-purpose parallel programmer are executed based on writer addresses.
MB90335 series 65 ? register list flash memory control status register (fmcs) flash memory program control register (fwr0) flash memory program control register (fwr1) sector conversion setting register (ssr0) note : when writing to ssr0 register, write ?0? except for sen0. initial value address : 0000ae h 000x0000 b initial value address : 00790c h 00000000 b initial value address : 00790d h 00000000 b initial value address : 00790e h 00xxxxx0 b ( r/w ) ( r/w ) ( r ) ( w ) ( r/w ) ( w ) ( r/w ) 76543210 rdyint ( r/w ) inte we rdy lpm1 lpm0 reserved reserved ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 76543210 sa6e ( r/w ) sa7e sa5e sa4e sa3e sa2e sa1e sa0e ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) ( r/w ) 15 14 13 12 11 10 9 0 ? ( r/w ) ???? ? sa9e sa8e ( r/w ) ( ? )( ? )( ? )( ? )( ? ) ( r/w ) 76543210 ? ( r/w ) ???? ?? sen0
MB90335 series 66 ? standard configuration for fujitsu standard serial on-board writing the flash microcontroller programmer (af220/af210/af120/af110) made by yokogawa digital computer corp. is used for fujitsu standard serial on-board writing. note : inquire of yokogawa digital computer corporation for details about the functions and operations of the flash microcontroller programmer (af220, af210, af120 and af110) , general-purpose common cable for connection (az210) and connectors. ? pins used for fujitsu standard serial on-board programming pin function description md2, md1, md0 mode input pin the device enters the serial program mode by setting md2 = 1, md1 = 1 and md0 = 0. x0, x1 oscillation pin because the internal cpu operation clock is set to be the 1 multiplication pll clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. p60, p61 write program start pins input a low level to p60 and a high level to p61. rst reset input pin ? sin0 serial data input pin uart0 is used as clk synchronous mode. in write mode, the pins used for the uart0 clk synchronous mode are sin0, sot0, and sck0. sot0 serial data output pin sck0 serial clock input pin v cc power source input pin when supplying the write voltage (mb90f337 : 3.3 v 0.3 v) from the user system, connection with the flash microcontroller programmer is not necessary. when connecting, do not short-circuit with the user power supply. v ss gnd pin share gnd with the flash microcontroller programmer. rs232c host interface cable (az201) general-purpose common cable (az210) clk synchronous serial mb90f337 user system can operate stand-alone flash microcontroller programmer + memory card
MB90335 series 67 the control circuit shown in the figure is required for using the p60, p61, sin0, sot0 and sck0 pins on the user system. isolate the user circuit during serial on-board writing, with the /tics signal of the flash microcontroller programmer. control circuit the mb90f337 serial clock frequency that can be input is determined by the following expression. use the flash microcontroller programmer to change the serial clock in put frequency setting dependi ng on the oscillator clock frequency to be used. inputable serial clock frequency = 0.125 oscillation clock frequency. ? maximum serial clock frequency ? system configuration of the flash microcontroller progra mmer (af220/af210/af120/af110) (made by yokogawa digital computer corp.) contact to : yokogawa digital computer corporation tel : 81-423-33-6224 note : the af200 flash microcontroller programmer is a retired product, but it can be supported using control module ff201. oscillation clock frequency maximum serial clock frequency acceptable to the flash microcontroller maximum serial clock frequency that can be set with the af220/af210/ af120/af110 maximum serial clock frequency that can be set with the af200 at 6 mhz 750 khz 500 khz 500 khz part number function unit af220/ac4p model with internal ethernet interface /100 v to 220 v power adapter af210/ac4p standard model /100 v to 220 v power adapter af120/ac4p single key internal ethernet interface mode /100 v to 220 v power adapter af110/ac4p single key model /100 v to 220 v power adapter az221 pc/at rs232c cable for writer az210 standard target probe (a) length : 1 m ff201 control module for fujitsu microelectronics f 2 mc-16lx flash microcontroller control mod- ule az290 remote controller /p2 2 mb pc card (option) flash memory capacity to respond to 128 kb /p4 4 mb pc card (option) flash memory capacity to respond to 512 kb 10 k ? af220/af210/af120/af110 write control pin af220/af210/af120/af110 /tics pin mb90f337 write control pin user
MB90335 series 68 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = 0.0 v. *2 : v i and v o must not exceed v cc + 0.3 v. however, if the maximum curren t to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *3 : applicable to pins : p60 to p67, utest (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 4.0 v input voltage* 1 v i v ss ? 0.3 v ss + 4.0 v *2 v ss ? 0.3 v ss + 6.0 v n-ch open-drain (withstand voltage i/o of 5 v)* 3 ? 0.5 v ss + 4.5 v usb i/o output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *2 ? 0.5 v ss + 4.5 v usb i/o maximum clamp current i clamp ? 2.0 + 2.0 ma *4 total maximum clamp current ? i clamp ?? 20 ma *4 ?l? level maximum output current i ol1 ? 10 ma other than usb i/o* 5 i ol2 ? 43 ma usb i/o* 5 ?l? level average output current i olav1 ? 4ma*6 i olav2 ? 15/4.5 ma usb-io (full speed/low speed) * 6 ?l? level maximum total output current i ol ? 100 ma ?l? level average total output current i olav ? 50 ma *7 ?h? level maximum output current i oh1 ? ? 10 ma other than usb i/o* 5 i oh2 ? ? 43 ma usb i/o* 5 ?h? level average output current i ohav1 ? ? 4ma*6 i ohav2 ?? 15/ ? 4.5 ma usb-io (full speed/low speed) * 6 ?h? level maximum total output current i oh ? ? 100 ma ?h? level average total output current i ohav ? ? 50 ma *7 power consumption pd ? 270 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c ? 55 + 125 c usb i/o
MB90335 series 69 (continued) *4 : ? applicable to pins: p00 to p07, p10 to p17, p20 to p27, p40 to p47, p50 to p54 ? use within recommended operating conditions. ? use at dc voltage (current) ? the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power su pply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than p60 to p67, dvp, dvm, hvp, hvm, utest, hcon ? sample recommended circuits: *5 : a peak value of an applicable one pi n is specified as a maximum output current. *6 : the average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *7 : the average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
MB90335 series 70 2. recommended operating conditions (v ss = 0.0 v) * : applicable to pins : p60 to p67, utest warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.0 3.6 v at normal operation (when using usb) 2.7 3.6 v at normal operation (when not using usb) 1.8 3.6 v hold state of stop operation input ?h? voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs1 0.8 v cc v cc + 0.3 v cmos hysteresis input pin v ihs2 0.8 v cc v ss + 5.3 v n-ch open-drain (withstand voltage i/o of 5 v)* v ihm v cc ? 0.3 v cc + 0.3 v md pin input v ihusb 2.0 v cc + 0.3 v usb pin input input ?l? voltage v il v ss ? 0.3 0.3 v cc v cmos input pin v ils v ss ? 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss ? 0.3 v ss + 0.3 v md pin input v ilusb v ss 0.8 v usb pin input differential input sensitivity v di 0.2 ? v usb pin input differential common mode input voltage range v cm 0.8 2.5 v usb pin input operating temperature t a ? 40 + 85 c when not using usb 0 + 70 c when using usb
MB90335 series 71 3. dc characteristics (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max output ?h? voltage v oh output pins other than p60 to p67, hvp, hvm, dvp, dvm i oh = ? 4.0 ma v cc ? 0.5 ? vcc v hvp, hvm, dvp, dvm r l = 15 k ? 5 % 2.8 ? 3.6 v output ?l? voltage v ol output pins other than hvp, hvm, dvp, dvm i ol = 4.0 ma vss ? vss + 0.4 v hvp, hvm, dvp, dvm r l = 1.5 k ? 5 % 0 ? 0.3 v input leak current i il output pins other than p60 to p67, hvp, hvm, dvp, dvm v cc = 3.3 v, vss < v i < v cc ? 10 ? + 10 a hvp, hvm, dvp, dvm ?? 5 ? + 5 a pull-up resistance r pull p00 to p07, p10 to p17 v cc = 3.3 v, t a = + 25 c 25 50 100 k ? open drain output current i liod p60 to p67 ?? 0.1 10 a power supply current i cc v cc v cc = 3.3 v, internal frequency 24 mhz, at normal operating at usb operating (ustp = 0) ? 55 65 ma mb90f337 ? 50 60 ma mb90337 v cc = 3.3 v, internal frequency 24 mhz, at normal operating at non-operating usb (ustp = 1) ? 50 60 ma mb90f337 ? 45 55 ma mb90337 i ccs v cc = 3.3 v, internal frequency 24 mhz, at sleep mode ? 25 40 ma i cts v cc = 3.3 v, internal frequency 24 mhz, at timer mode ? 3.5 10 ma v cc = 3.3 v, internal frequency 3 mhz, at timer mode ? 1.0 2.0 ma i cch t a = + 25 c, at stop mode ? 140 a
MB90335 series 72 (continued) (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) note : p60 to p67 are n-ch open-drain pins usually used as cmos. parameter sym- bol pin name conditions value unit remarks min typ max input capacitance c in other than vcc and vss ?? 515pf pull-up resistor r up rst ? 25 50 100 k ? pull-down resistor r down md2 v cc = 3.0 v at t a = + 25 c 25 50 100 k ? mb90337 usb i/o output impedance z usb dvp, dvm hvp, hvm ? 3 ? 14 ?
MB90335 series 73 4. ac characteristics (1) clock input timing (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name value unit remarks min typ max clock frequency f ch x0, x1 ? 6 ? mhz when oscillator is used 6 ? 24 mhz external clock input clock cycle time t hcyl x0, x1 ? 166.7 ? ns when oscillator is used 166.7 ? 41.7 ns external clock input input clock pulse width p wh p wl x0 10 ?? ns a reference duty ratio is 30 % to 70 % . input clock rise time and fall time tcr tcf x0 ?? 5 ns at external clock internal operating clock frequency f cp ? 3 ? 24 mhz when main clock is used internal operating clock cycle time t cp ? 42 ? 333 ns when main clock is used 0.8 v cc 0.2 v cc t cf t cr t hcyl p wh p wl x0 ? clock timing
MB90335 series 74 the ac standards provide that the following measurement reference voltages. ? pll operation guarantee range relation between power supply voltage and internal operation clock frequency note : when the usb is used, operation is guaranteed at voltages between 3.0 v to 3.6 v. relation between internal operation clock frequency and external clock frequency 3.6 3.0 2.7 3 6 12 24 internal clock f cp (mhz) power supply voltage v cc (v) pll operation guarantee range normal operation assurance range 3 12 6 6 24 24 internal clock f cp (mhz) external clock f c (mhz) 4 x 2 x 1 x external clock 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hysteresis input pin hysteresis input/other than md input pin ? output signal waveform output pin
MB90335 series 75 (2) reset (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) * : oscillation time of oscillator is th e time that the amplitude reaches 90 %. it takes several milliseconds to several dozens of milliseconds on a crystal o scillator, several hundreds of micros econds to several milliseconds on a ceramic oscillator, and 0 milliseconds on an external clock. parameter sym- bol pin name conditions value unit remarks min max reset input time t rstl rst ? 500 ? ns at normal operating, at time base timer mode, at main sleep mode, at pll sleep mode oscillation time of oscillator* + 500 ns ? s at stop mode r s t x0 500 n s t r s tl 0.2 v cc 0.2 v cc r s t t r s tl 0.2 v cc 0.2 v cc ? during stop mode internal operation clock internal reset oscillation time of oscillator oscillation stabilization wait time execute instruction 90 % of amplitude ? during normal operation, time-base timer mode, main sleep mode and pll sleep mode
MB90335 series 76 (3) power-on reset (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? v cc must be lower than 0.2 v before the power supply is turned on. ? the above standard is a value for performing a power-on reset. ? in the device, there are internal registers which is in itialized only by a power-on reset. when the initial ization of these items is expected, turn on the power supply according to the standards. note : sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during operatio n as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. when raising the power, do not use pll clock. however, if voltage drop is 1 v/s or less, use of pll clock is allowed during operation. parameter symbol pin name conditions value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply shutdown time t off v cc 1 ? ms waiting time until power-on v cc t r 0.2 v 0.2 v 2.7 v t off 0.2 v v cc 3 .0 v v ss ram data hold the rising edge should be 50 mv/ms or less.
MB90335 series 77 (4) uart0, uart1 i/o extended serial timing (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? above rating is the case of clk synchronous mode. ? c l is a load capacitance value on pins for testing. ? t cp is the machine cycle period (unit : ns) . refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sckx internal shift clock mode output pin is c l = 80 pf + 1 ttl 8 t cp ? ns sck sot delay time t slov sckx sotx ? 80 + 80 ns valid sin sck t ivsh sckx sinx 100 ? ns sck valid sin hold time t shix sckx sinx 60 ? ns serial clock h pulse width t shsl sckx, sinx external shift clock mode output pin is c l = 80 pf + 1 ttl 4 t cp ? ns serial clock l pulse width t slsh sckx, sinx 4 t cp ? ns sck sot delay time t slov sckx sotx ? 150 ns valid sin sck t ivsh sckx sinx 60 ? ns sck valid sin hold time t shix sckx sinx 60 ? ns ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
MB90335 series 78 (5) i 2 c timing (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : f cp is internal operating clock frequency. refer to ? (1) clock input timing?. *2 : r and c are pull-up resistance of scl and sda lines and load capacitance. *3 : the maximum t hddat only has to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *4 : refer to ? ? note of sda, scl set-up time?. parameter symbol conditions value unit min max scl clock frequency f scl power-supply of external pull-up resistor at 5.0 v r = 1.2 k ? , c = 50 pf* 2 power-supply of external pull-up resistor at 3.6 v r = 1.0 k ? , c = 50 pf* 2 0 100 khz (repeat) [start] condition hold time sda scl t hdsta 4.0 ? s scl clock ?l? width t low 4.7 ? s scl clock ?h? width t high 4.0 ? s repeat [start] condition setup time scl sda t susta 4.7 ? s data hold time scl sda t hddat 03.45* 3 s data setup time sda scl t sudat power-supply of external pull-up resistor at 5.0 v f cp * 1 20 mhz, r = 1.2 k ? , c = 50 pf* 2 power-supply of external pull-up resistor at 3.6 v f cp * 1 20 mhz, r = 1.0 k ? , c = 50 pf* 2 250* 4 ? ns power-supply of external pull-up resistor at 5.0 v f cp * 1 > 20 mhz, r = 1.2 k ? , c = 50 pf* 2 power-supply of external pull-up resistor at 3.6 v f cp * 1 > 20 mhz, r = 1.0 k ? , c = 50 pf* 2 200* 4 ? [stop] condition setup time scl sda t susto power-supply of external pull-up resistor at 5.0 v r = 1.2 k ? , c = 50 pf* 2 power-supply of external pull-up resistor at 3.6 v r = 1.0 k ? , c = 50 pf* 2 4.0 ? s bus free time between [stop] condition and [s tart] condition t bus 4.7 ? s
MB90335 series 79 note : the rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. be sure to adjust the pull-up resistor of sda and scl if the rating of the input data set-up time cannot be satisfied. sda scl 6 tcp ? note of sda, scl set-up time input data set-up time sda scl t low t hdsta t hddat t sudat t susta t susto t hdsta t high t bus ? timing definition
MB90335 series 80 (6) timer input timing (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp is the machine cycle period (unit : ns) . refer to ? (1) clock input timing?. (7) timer output timing (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) (8) trigger input timing (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp is the machine cycle period (unit : ns) . refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max input pulse width t tiwh t tiwl pwc ? 4 t cp ? ns parameter symbol pin name conditions value unit min max clk t out change time ppg0 to ppg3 change time t to ppgx ? 30 ? ns parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl intx ? 5 t cp ? ns at normal operating 1 ? sat stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl pwc clk ppgx 2.4 v t to 2.4 v 0.8 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl intx
MB90335 series 81 5. usb characteristics (v cc = 3.3 v 0.3 v, v ss = 0.0 v, t a = 0 c to + 70 c) * : arrange the series resistance rs values in order to set the impedance value within the output impedance zsrv. ? data signal timing (full speed) ? data signal timing (low speed) parameter symbol sym- bol value unit remarks min max input characteristics input high level voltage v ih 2.0 ? v input low level voltage v il ? 0.8 v differential input sensitivity v di 0.2 ? v differential common mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 3.6 v i oh = ? 200 a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross over voltage v crs 1.3 2.0 v rise time t fr 4 20 ns full speed t lr 75 300 ns low speed fall time t ff 4 20 ns full speed t lf 75 300 ns low speed rising/falling time matching t rfm 90 111.11 % (t fr /t ff ) t rlm 80 125 % (t lr /t lf ) output impedance z drv 28 44 ? including rs = 27 ? series resistance r s 25 30 ? recommended value = 27 ? at using usb* dvm/hvm 90% t fr 10% 90% 10% t ff vcrs dvp/hvp rise time fall time hvp 90% t lr 10% 90% 10% tlf vcrs hvm rise time fall time
MB90335 series 82 ? load condition (full speed) ? load condition (low speed) dvp/hvp r s = 27 ? c l = 50 pf dvm/hvm r s = 27 ? z usb z usb c l = 50 pf testing point testing point h v p r s = 27 ? c l = 50 pf 150 pf h v m r s = 27 ? c l = 50 pf 150 pf z usb z usb testing point testing point
MB90335 series 83 6. flash memory write/erase characteristics * : this value comes from the technology qualification. (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) parameter condition value unit remarks min typ max sector erase time (4 kbytes sector) t a = + 25 c v cc = 3.0 v ? 0.2 0.5 s excludes 00 h programming prior to erasure. sector erase time (16 kbytes sector) ? 0.5 7.5 s excludes 00 h programming prior to erasure. chip erase time ? 2.6 ? s excludes 00 h programming prior to erasure. word (8 bits width) programming time ? 16 3600 s except for over head time of system program/erase cycle ? 10000 ?? cycle flash data retention time average t a = + 85 c 20 ?? year *
MB90335 series 84 ordering information part number package remarks mb90f337pfm mb90337pfm 64-pin plastic lqfp (fpt-64p-m09) mb90v330a 299-pin ceramic pga (pga-299c-a01) for evaluation
MB90335 series 85 package dimension please confirm the la test package dimens ion by following url. http://edevice.fujitsu.com/package/en-search/ 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12 12 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m09) (fpt-64p-m09) c 200 3 fujit s u limited f6401 8s -c- 3 -5 0.65(.026) 0.10(.004) 116 17 3 2 49 64 33 4 8 12.000.10(.472.004) s q 14.000.20(.551.00 8 ) s q index 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) 0.1450.055 (.0057.0022) "a" .059 ?.004 +.00 8 ?0.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) 0.10(.004) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
MB90335 series 86 main changes in this edition (continued) page section change results 4 product lineup changed vbus to utest. 5 pin assignment 7 pin description pin no. 56, 57, 58 changed the description; data input pin for simple serial i/o data input pin for extended i/o serial interface pin no. 1 for pin name, vbus utest for status at reset/ function, vbus utest input for function, ? status detection pin of usb cable (withstand voltage of 5 v)? ?usb test pin. connect this to a pull-down resistor during normal usage.? 10 handling devices 5. about crystal oscillator circuit added at the end of the section; please ask the crystal maker to evaluate the oscillational characteristic s of the crystal and this device. 12 block diagram changed vbus to utest. 16 i/o map address 000060 h for the register, pwc div iding ratio register pwc dividing ratio control register 17 address 000072 h for the register, i 2 c bus clock selection register i 2 c bus clock control register address 0000a0 h for the register, low power consumption mode register low power consumption mode control register address 0000a8 h for the register, watchdog control register watchdog timer control register address 0000ae h for the register abbreviation, fmcr fmcs 18 address 0000d1 h prohibited udc control register 19 address 0000d2 h for the initial value, x1000000 b 01000000 b address 0000d3 h for the initial value, xxxx000x b xxxx0000 b address 0000df h for the initial value, 00000000 b xxxxx000 b address 0000e0 h for the initial value, 00000000 b xx000000 b address 0000e4 h for the initial value, xxxxxxxx b 0xxxxxxx b address 0000e5 h for the initial value, 100xx00x b 100xx000 b address 0000e9 h , 0000eb h , 0000ed h , 0000ef h for the initial value, 1000000x b 10000000 b 20 address 00790c h for the register, flash program control register 0 flash memory program control register 0 address 00790d h for the register, flash program control register 1 flash memory program control register 1
MB90335 series 87 (continued) page section change results 22 interrupt sources, interrupt vectors, and interrupt control registers. usb function 2 for the dmac, ?2 to 6? ?2 to 6* 2 ?. 23 added the footnote of *2. content of usb interruption factor usb function 2 added the ? * ? and its footnote. usb function 3 deleted the voff, von. 34 peripheral resources 5. multifunction timer ? 8/16-bit ppg timer ppg control register (ppgc0 to ppgc3) ppg operation mode control register (ppgc0 to ppgc3) ppg clock control regi ster (pcs01, pcs23) ppg output control register (ppg01, ppg23) 38 ? pwc timer ratio of dividing frequency control register (divr) pwc ratio of dividing frequency control register (divr) 41 6. uart serial input/output register (sidr0, sidr1/sodr0, sodr1) serial input/output data register (sidr0, sidr1/sodr0, sodr1) serial data register (ssr0, ssr1) serial status register (ssr0, ssr1) 45 8. i 2 c interface i 2 c bus clock selection register (iccr0) i 2 c bus clock control register (iccr0) 47 9. usb function deleted the following list; ? capable of detection of connection and disconnection by monitoring the usb bus power line. changed the regist er list in udc control register (udcc) and ep0 control register (ep0c). 48 changed the register list in time stamp register (tmsp), udc status register (udcs), and udc interrupt enable register (udcie). 49 for ep0o status register (ep0os), changed to ?reserved? for the bit8 and bit7 and changed the initial value. for ep1 status register (ep1s), changed to ?reserved? for the bit12 and changed (r/w) to (r) in the bit8 to bit0. for ep2/3/4/5 status register (ep2s to ep5s), changed to ?reserved? for bit12, bit8, bit7, (r/w) to (r) for the bit6 to bit0, and changed the initial values. 51 10. usb mini-host deleted all of the ?usb? from the register names. changed the ?usb retry timer setting register 0/1/2 (hrtimer)? to ?retry timer setting register (hrtimer)?.
MB90335 series 88 (continued) the vertical lines marked in the left side of the page show the changes. page section change results 52 peripheral resources 10. usb mini-host deleted all of the ?usb? from the register names. changed the ?usb eof setting register 0/1 (heof)? to ?eof setting register (heof)?. changed the ?usb token end point register (htoken)? to ?host token end point register (htoken)?. 65 19. 512 kbits flash memory flash memory control register (fmcs) flash memory control status register (fmcs) 68 electrical characteristics 1. absolute maximum ratings for ?l? level average output current, i olav ?3? i olav1 ?4?, i olav2 ?15/4.5? for ?l" level maximum total output current, i ol ?60? i ol ?100? for ?l? level average total output current, i olav ?30? i olav ?50? for ?h? level average output current, i ohav ? ? 3? i ohav1 ? ? 4?, i ohav2 ? ? 15/ ? 4.5? for ?h? level maximum total output current, i oh ? ? 60? i oh ? ? 100? for ?h? level average total output current, i ohav ? ? 30? i ohav ? ? 50? changed the footnote *3 ?applicable to pins : p60 to p67, vbus? to ?applicable to pins : p60 to p67, utest? 69 changed the ?vbus? to ?utest? in the footnote *4 ? ? note that analog system input/output pins other than p60 to p67, dvp,dvm, hvp, hvm, utest, hcon ?. 70 2. recommended operating conditions deleted the ?series resistance?. changed the ?vbus? to ?utest? in the footnote. 72 3. dc characteristics added the ?usb i/o output impedance?. 76 4. ac characteristics (3) power-on reset changed the minimum value of the ?power supply rising time? : ? ? ? ?0.05? 78 (5) i 2 c timing added ?*4? to the minimum value in the ?data setup time sda scl ? added the footnote : *4 : refer to ? ? note of sda, scl set-up time?. 81 5. usb characteristics for the symbol of parameter, output resistance of output characteristics output impedance of out- put characteristics. added the ?series resistance?. 82 changed the figures of ? ? load condition (full speed)? and ? ? load condition (low speed)? 84 ordering information added the mb90v330a.
MB90335 series 89 memo
MB90335 series 90 memo
MB90335 series 91 memo
fujitsu microelectronics limited shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. 151 lorong chuan, #05-08 new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu microelectronics shanghai co., ltd. rm.3102, bund center, no.222 yan an road(e), shanghai 200002, china tel: +86-21-6335-1560 fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road tsimshatsui, kowloon hong kong tel: +852-2377-0226 fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porat- ing the device based on such in formation, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use acco mpanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuc lear reaction control in nuclear facility, airc raft flight control, air traffic c ontrol, mass transport control, me dical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high re liability (i.e ., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited strategic business development dept.

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